View M41T00CAP_5355803.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. march 2012 doc id 14557 rev 5 1/27 1 M41T00CAP serial access real-time clock (rtc) with integral backup battery and crystal datasheet ? production data features real-time clock (rtc) with backup battery integrated into package uses m41t00s enhanced rtc with precision switchover reference 400 khz i 2 c serial interface automatic switchover and deselect circuitry with fixed reference voltage ?v cc = 2.7 to 5.5 v operating voltage range ? 2.6 v (typ) power-fail deselect (switchover) threshold counters for seconds, minutes, hours, day, date, month, year and century software clock calibration low operating current of 300 a oscillator stop detection battery backup operating temperature of 0 to 70 c self-contained batt ery and crystal in caphat? dip package rohs compliant ? lead-free second level interconnect 24 1 pcdip24 (pc) battery/crystal caphat tm www.st.com
contents M41T00CAP 2/27 doc id 14557 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M41T00CAP contents doc id 14557 rev 5 3/27 9 environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of tables M41T00CAP 4/27 doc id 14557 rev 5 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. timekeeper ? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 9. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. pcdip24 ? 24-pin plastic dip, battery caph at?, package mechanical data . . . . . . . . . 23 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M41T00CAP list of figures doc id 14557 rev 5 5/27 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. pcdip24 ? 24-pin plastic dip, battery caphat?, package outline . . . . . . . . . . . . . . . . . 23 figure 16. recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
description M41T00CAP 6/27 doc id 14557 rev 5 1 description the M41T00CAP is a low-power serial real-time clock (rtc) with integral battery and crystal in st?s 24-pin caphat? package. it includes a crystal controlled, 32.768 khz oscillator and has a built-in power sense circuit which detects power failures and automatically switches to the backup battery when a power failure occurs. eight registers comprise the clock/calendar function and are configured in binary-coded decimal (bcd) format. addresses and data are transferred serially via an industry standard, two line, 400 khz, bidirectional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. the internal lithium coin cell contains ample energy to sustain timekeeping operation for 10 years in the absence of system power. the eight clock address locations contain the century, year, month, date, day, hour, minute, and second in 24-hour bcd format. corrections for the number of days in a month, including leap year, are made automatically (leap year valid up to year 2100). figure 1. logic diagram s cl v cc M41T00CAP v ss s da ft/out ai09165
M41T00CAP pin settings doc id 14557 rev 5 7/27 2 pin settings 2.1 pin connection figure 2. dip connections 1. du is ?don?t use?. do not connect. must be allowed to float. do not connect to v cc or v ss . 2.2 pin description nc nc nc nc nc nc nc nc nc nc ft/out nc nc nc nc nc scl nc nc du v ss sda nc v cc ai01028 M41T00CAP 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13 (1) table 1. pin description symbol name and function ft/out frequency test / output driver (open drain) sda serial data input/output scl serial clock input v cc supply voltage v ss ground du (1) 1. du is ?don?t use?. do not connect. must be allowed to float. do not connect to v cc or v ss . do not use. do not connect. reserved for factory use. nc no connection
pin settings M41T00CAP 8/27 doc id 14557 rev 5 figure 3. block diagram 1. open drain output real time clock calendar rtc & calibration frequency test oscillator fail circuit logic output ft/out (1) internal power ft out sda scl v cc compare i 2 c interface 32khz oscillator v bat crystal v so v pfd ai09168 write protect
M41T00CAP operation doc id 14557 rev 5 9/27 3 operation the M41T00CAP clock operates as a slave device on the i 2 c serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 8 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. year register 8. calibration register the M41T00CAP clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the de vice will not be recognized at th is time to prevent erroneous data from being written to the device from a an out-of-tolerance system. once v cc falls below the switchover voltage (v so ), the device automatically switches over to the battery and powers down into an ultra-low current mode of operation to prolong battery life. if v bat is less than v pfd , the device power is switched from v cc to v bat when v cc drops below v bat . if v bat is greater than v pfd , the device power is switched from v cc to v bat when v cc drops below v pfd . upon power-up, the device switches from battery to v cc at v so . when v cc rises above v pfd , the inputs will be recognized. for more information on battery storage life refer to application note an1012. 3.1 wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bidirectional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 3.2 bus not busy both data and clock lines remain high.
operation M41T00CAP 10/27 doc id 14557 rev 5 3.3 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 3.4 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 3.5 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 3.6 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the master transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
M41T00CAP operation doc id 14557 rev 5 11/27 figure 4. serial bus data transfer sequence figure 5. acknowledgement sequence 3.7 read mode in this mode the master reads the M41T00CAP slave after setting the slave address (see figure 7 ). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w = 1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and the mast er receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the M41T00CAP slave transmitter will now place th e data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). the updating will resume upon a stop co ndition or when the pointer increments to an y non-clock address (07h). note: this is true both in read mode and write mode. ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
operation M41T00CAP 12/27 doc id 14557 rev 5 an alternate read mode may also be implemented whereby the master reads the m41t00s slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 8 ). figure 6. slave address location figure 7. read mode sequence figure 8. alternative read mode sequence ai00602 r/w s lave addre ss s ta rt a 01000 11 m s b l s b ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n + 1 data n+x word address (an) slave address s start r/w slave address ack ai00 8 95 bu s activity: ack s ack ack ack no ack s top s ta rt p s da line bu s activity: ma s ter r/w data n data n+1 data n+x s lave addre ss
M41T00CAP operation doc id 14557 rev 5 13/27 3.8 write mode in this mode the master transmitter transmits to the M41T00CAP slave receiver. bus protocol is shown in figure 9 . following the start condition and slave address, a logic '0' (r/w=0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on-chip add ress pointer. th e data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge cloc k. the device slave receiver will send an acknowledge clock to the master transm itter after it has received the slave address and again after it has received the word address and after each data byte. figure 9. write mode sequence 3.9 data retention mode with valid v cc applied, the M41T00CAP can be accessed as described above with read or write cycles. should the supply voltage decay, the power input will be switched from the v cc pin to the battery when v cc falls below the battery backup switchover voltage (v so ). at this time the clock registers will be ma intained by the internal battery supply. on power-up, when v cc returns to a nominal value, write protection continues for t rec after v cc rises above v so . ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
clock operation M41T00CAP 14/27 doc id 14557 rev 5 4 clock operation the 8-byte register map (see ta b l e 2 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 02h (century/hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its init ial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 03h contain the day (day of week). registers 04h, 05h, and 06h contain the date (day of month), month and years. the eighth clock register is the calibration register (this is described in the clock calibration section). bit d7 of register 00h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restar ts within one second. the seven clock registers may be read one byte at a time, or in a sequential block. the calibration register (address location 07h) may be accessed independently. provision has been made to ensure that a clock update does not occur while any of the seven clock addresses are being read. if a clock address is being r ead, an update of the clock regist ers will be halted. this will prevent a transition of data during the read. keys: 0 = must be set to '0' cb = century bit ceb = century enable bit ft = frequency test bit of = oscillator fail bit out = output level s = sign bit st = stop bit table 2. timekeeper ? register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h st 10 seconds seconds seconds 00-59 01h of 10 minutes minutes minutes 00-59 02h ceb cb 10 hours hours (24-hour format) century/hours 0-1/00-23 03h00000 day of week day 01-7 04h 0 0 10 date date: day of month date 01-31 05h 0 0 0 10m month month 01-12 06h 10 years year year 00-99 07h out ft s calibration calibration
M41T00CAP clock operation doc id 14557 rev 5 15/27 4.1 clock registers the M41T00CAP has 8 internal registers which contain clock and calibration data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). the update will resume either due to a stop condition or when the pointer increments to any non- clock address (07h). clock registers store data in bcd. the calibration register stores data in binary format. the internal divider (or cloc k) chain will be reset upon the completion of a write to any clock address. 4.2 calibrating the clock the M41T00CAP is driven by a quartz-contr olled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 23 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1 minute per month (see figure 10 ). when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals ch anges with temperature. the M41T00CAP design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 11 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. adding counts speeds th e clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the calibration register 07h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829,120 actual oscillator cycles, that is +4.0 68 or ?2.034 ppm of adjustme nt per calibration step in the calibration register (see figure 11 ). assuming that the oscillato r is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total possible adjustment range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given M41T00CAP may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?timekeeper ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the environment requires , even if the final product is packaged in a non-user servicea ble enclosure. the designer could provide a simple utility that accesses the calibration byte. the second appr oach is better suited to a manufacturing environment, an d involves the use of the ft/out pin. the pin will toggle at 512 hz, when the stop bit (st, d7 of 00h) is '0,' and the frequency test bit (ft, d6 of 07h) is '1.' any deviation from 512 hz indicates the degree and direction of osc illator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the ca libration byte
clock operation M41T00CAP 16/27 doc id 14557 rev 5 for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the ft/out pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500-10 k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down. figure 10. crystal accuracy across temperature figure 11. clock calibration 4.3 century bit bits d7 and d6 of clock register 02h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, ei ther from a '0' to '1' or from '1' to '0' at the turn of the century (dependi ng upon its initial state). if ce b is set to a '0,' cb will not toggle. ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal po s itive calibration negative calibration
M41T00CAP clock operation doc id 14557 rev 5 17/27 4.4 oscillator fail detection if the oscillator fail bit (of) is in ternally set to '1,' this indica tes that the osc illator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' this will restart the oscillator. the following co nditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). the voltage present on v cc is insufficient to support oscillation. the st bit is set to '1'. external interference of the crystal. the of bit will remain set to '1' until written to logic '0.' the oscillator must have started and run for at least 4 seconds before attempting to reset the of bit to '0.' 4.5 output driver pin when the ft bit is not set, the ft/out pin becomes an output driver that reflects the contents of d7 of the calibration register. in other words, when d7 (out bit) and d6 (ft bit) of address location 07 h are '0's, then the ft/out pin will be driven low. note: the ft/out pin is an open drain which requires an external pull-up resistor. 4.6 initial power-on default upon initial application of power to the device, the st and ft bits are set to a '0' state, and the of and out bits will be set to a '1.' all ot her register bits will in itially power on in a random state (see ta b l e 3 ). table 3. preferred default values condition st out ft of initial power-up (1) 1. state of other control bits undefined. 0101 subsequent power-up (with battery backup) (2) 2. uc = unchanged uc uc 0 uc
maximum ratings M41T00CAP 18/27 doc id 14557 rev 5 5 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. caution: negative undershoots below ?0.3 volts are not allowed on any pin while in the battery backup mode. table 4. absolute maximum ratings sym parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 7 v t sld (1)(2) 1. soldering temperature of the ic leads is to not exc eed 260 c for 10 seconds. in order to protect the lithium battery, preheat temperatures must be limited such t hat the battery temperature does not exceed +85 c. furthermore, the devices shall not be exposed to ir reflow. 2. for dip packaged devices, ul trasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to v cc +0.3 v i o output current 20 ma p d power dissipation 1 w
M41T00CAP dc and ac parameters doc id 14557 rev 5 19/27 6 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in ta bl e 5 : operating and ac measurement conditions . designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. note: output hi-z is defined as the point where data is no longer driven. figure 12. ac measurement i/o waveform table 5. operating and ac measurement conditions parameter M41T00CAP supply voltage (v cc ) 2.7 to 5.5 v ambient operating temperature (t a ) 0 to 70 c load capacitance (c l )100 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc input and output timing ref. voltages 0.3 v cc to 0.7 v cc table 6. capacitance symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 5 v; sampled only, not 100% tested. 2. at 25 c, f = 1 mhz. min max unit c in input capacitance - 7 pf c out (3) 3. outputs deselected. output capacitance - 10 pf t lp low-pass filter input time constant (sda and scl) - 50 ns ai0256 8 0. 8 v cc 0.2v cc 0.7v cc 0. 3 v cc
dc and ac parameters M41T00CAP 20/27 doc id 14557 rev 5 figure 13. power down/up mode ac waveforms table 7. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). min typ max unit i li input leakage current 0v v in v cc -1a i lo output leakage current 0v v out v cc -1a i cc1 supply current switch freq = 400 khz - 300 a i cc2 supply current (standby) scl = 0 hz all inputs v cc ? 0.2 v v ss + 0.2 v -70a v il input low voltage ?0.3 - 0.3 v cc v v ih input high voltage 0.7 v cc - v cc + 0.3 v v ol output low voltage i ol = 3.0 ma -0.4v output low voltage (open drain) (2) 2. for ft/out pin (open drain). i ol = 10 ma -0.4v pull-up supply voltage (open drain) (2) -5.5v table 8. power down/up ac characteristics symbol parameter (1)(2) 1. v cc fall time should not exceed 5 mv/s. 2. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). min typ max unit t pd scl and sda at v ih before power down 0 - - ns t rec scl and sda at v ih after power up 10 - - s ai00596 v cc trec tpd v so sda scl don't care
M41T00CAP dc and ac parameters doc id 14557 rev 5 21/27 figure 14. bus timing requirements sequence table 9. power down/up trip points dc characteristics sym parameter (1)(2) min typ max unit v pfd power-fail deselect 2.5 2.6 2.7 v hysteresis 25 mv v so battery backup switchover voltage v bat < v pfd v bat v v bat > v pfd v pfd v hysteresis 40 mv t dr (3) expected data retention time 10 years 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 2.7 to 5.5 v (except where noted). 3. t a = 25c, v cc = 0 v, oscillator on. ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
dc and ac parameters M41T00CAP 22/27 doc id 14557 rev 5 table 10. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). min typ max units f scl scl clock frequency 0 - 400 khz t low clock low period 1.3 - s t high clock high period 600 - ns t r sda and scl rise time - 300 ns t f sda and scl fall time - 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 - ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 - ns t su:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined re gion (300 ns max) of the falling edge of scl. data setup time 100 - ns t hd:dat data hold time 0 - s t su:sto stop condition setup time 600 - ns t buf time the bus must be free before a new transmission can start 1.3 - s
M41T00CAP package mechanical data doc id 14557 rev 5 23/27 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 15. pcdip24 ? 24-pin plastic dip, battery caphat?, package outline note: drawing is not to scale. pcdip a2 a1 a l b1 b e1 d e n 1 c ea e 3 table 11. pcdip24 ? 24-pin plastic dip, battery caphat?, package mechanical data symb mm inches ty p m i n m a x ty p m i n m a x a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 27.94 1.1 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24
part numbering M41T00CAP 24/27 doc id 14557 rev 5 8 part numbering table 12. ordering information scheme example: m41t 00cap pc 1 device type m41t supply voltage and write protect voltage 00cap = v cc = 2.7 to 5.5 v package pc = pcdip24 temperature range 1 = 0 c to 70 c shipping method blank = ecopack ? package, tubes
M41T00CAP environmental information doc id 14557 rev 5 25/27 9 environmental information figure 16. recycling symbols this product contains a non-rechargeable lithi um (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
revision history M41T00CAP 26/27 doc id 14557 rev 5 10 revision history table 13. document revision history date revision changes 28-jun-2006 1 first release 20-mar-2008 2 document status upgraded to full datasheet; updated title and cover page, section 1 , 3 , 4 , figure 1 , 2 , 3 , 4 , ta b l e 1 , 7 , 8 , 9 , 10 . 25-mar-2009 3 added section 9: environmental information ; updated text in section 7: package mechanical data . 27-may-2010 4 updated section 5 , ta b l e 1 1 ; reformatted document. 22-mar-2012 5 updated title of document; section 9: environmental information .
M41T00CAP doc id 14557 rev 5 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M41T00CAP

	To Download M41T00CAP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .